The present invention is directed to sense amplifiers, in general, and more particularly, to a dynamic sense amplifier for low-power applications.
In general, a sense amplifier is coupled through a connecting node to a multiplicity of logic cells, like memory cells, for example, to read the logic states thereof via the connecting node and pass the read data on to processing circuitry. For a memory matrix of logic cells, there may be a sense amplifier coupled to each row of the matrix for reading out data from each memory cell of the memory row to the processing circuitry. For a large memory, there would be a proportionately large number of sense amplifiers. Keeping power consumption of these sense amplifiers low in low-power applications is of paramount importance especially in battery-powered applications where battery lifetime is an important consideration.
This logic cell read process is carried out by each sense amplifier without disturbing the logic state of each connected cell. To minimize disturbing a logic cell during a read operation, a sense amplifier generally includes a circuit to limit the voltage occurring at its connecting node. If left unchecked, the voltage at the connecting node during a read operation would rise to the level Vdd of its power source, which is higher than a connected logic cell may withstand and remain undisturbed. In some applications, the sense amplifier includes a pass transistor at the connecting node, with the gate voltage thereof limited to a fraction of Vdd, like one-half Vdd, for example, by a voltage reference circuit.
Conventional voltage reference circuits are of the static type, like a resistance voltage divider circuit, for example, which produce a substantial DC current drain during read operations. While it is understood that resistive divider circuits can be designed to have lower static current draw, the speed of operation thereof then becomes a factor due to the resulting RC time constants. In fact, this is the primary reason why such circuits are not operated dynamically. Accordingly, the cumulative static current drain resulting from the read operations of the sense amplifiers contributes substantially to the overall power consumption of the particular circuit, which detracts from the intended low-power operation. Reducing the power dissipation of these sense amplifier voltage reference circuits would be considered a significant power savings improvement, especially useful for extending battery life in battery-powered applications.
The present invention proposes a sense amplifier which includes a dynamic voltage reference circuit especially suited for low-power applications, particularly battery-powered circuits. A dynamic sense amplifier has the attributes of being inherently high-speed as well as eliminating substantially static power dissipation. Thus, the improved voltage reference circuit not only reduces the power consumption of each sense amplifier, resulting in a substantial power savings, but retains the high-speed operation thereof.
In accordance with one aspect of the present invention, a sense amplifier comprises: a connecting node connectable to a plurality of logic cells for reading the logic states thereof; at least one output; circuitry for transferring the read logic states from the connecting node to the at least one output; and a circuit dynamically operative to limit the voltage at the connecting node substantially to a predetermined voltage.
In accordance with another aspect of the present invention, the sense amplifier includes a reactive impedance divider network operative to limit the voltage at the connecting node substantially to a predetermined voltage. In one embodiment, the reactive impedance divider network includes: a pass transistor coupled between the connecting node and the transferring circuit, and operative to conduct the logic states read from the logic cells to the transferring circuit; and a reactive impedance divider circuit coupled to a voltage source for producing at a node thereof the predetermined voltage as a fraction of the voltage of the source, the node being coupled to the pass transistor to limit the voltage at the connecting node substantially to the predetermined voltage.
In another embodiment, the reactive impedance divider circuit comprises a capacitive divider circuit coupled to the voltage source for producing at a node thereof the predetermined voltage as a fraction of the voltage of the source, the node being coupled to the gate drive of the pass transistor to limit the voltage at the connecting node substantially to the predetermined voltage. In yet another embodiment, the capacitive divider circuit is dynamically operative in charge and discharge states to produce the predetermined voltage at the node in accordance with a duty cycle of at least one clock signal.